The present invention, relates, to the field of dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) integrated circuit (xe2x80x9cICxe2x80x9d) memory devices and other ICs incorporating embedded DRAM arrays. More particularly, the present invention relates to a precharge and reference voltage technique for DRAM memory arrays which does not utilize a one half supply voltage level (xe2x80x9cVCC/2xe2x80x9d) reference voltage bit line precharge level.
As supply voltages continue to decrease, and the voltage differential between a logic level xe2x80x9c1xe2x80x9d and a logic level xe2x80x9c0xe2x80x9d further diminishes, the motivation to implement bit line precharge techniques other than a conventional one half supply voltage level (xe2x80x9cVCC/2xe2x80x9d) increases. In this regard, several VCC or VSS (circuit ground or reference voltage level) precharged bit line schemes have been designed into DRAMs over the years. In fact, some of the earliest DRAM designs utilized an analogous technique. The difficulty has, nevertheless remained in providing an acceptable and stable reference so that a logic level xe2x80x9c0xe2x80x9d with VSS precharged bit lines and a logic level xe2x80x9c1xe2x80x9d with VCC precharged bit lines can still be accurately sensed.
U.S. Pat. No. 6,111,803 issued Aug. 29, 2000 for: xe2x80x9cReduced Cell Voltage for Memory Devicexe2x80x9d to Derner et al. has proposed VCC precharged bit lines where charge bleeds off with the latch N-channel bar (xe2x80x9cLNBxe2x80x9d) node to generate a reference voltage. U.S. Pat. No. 4,669,065 issued May 26, 1987 for: xe2x80x9cDynamic Memory Apparatus Having a Sense Amplifier and a Reference Voltage Connection Circuit Thereforxe2x80x9d to Ohsawa describes a reference cell with an additional connection to the cell node to short two dummy cells together so that a VCC/2 reference voltage is generated and stored into each of the dummy cells.
Eto et al. xe2x80x9cA 1-Gb SDRAM with Ground-Level Precharged Bi Line and Nonboosted 2.1-V Word Linexe2x80x9d; IEEE Journal of Solid-State Circuits, Vol. 33, No. 11, November 1998 pp. 1697-1701 (See also: Eto et al. xe2x80x9cA 1-Gb SDRAM with Ground-Level Precharged Bi Line and Nonboosted 2.1-V Word Linexe2x80x9d; ISSCC98/Session 5/DRAM/Paper TP 5.6, pp 82-83, 419.) describes a grounded bit line precharge scheme wherein a reference level is generated by a metal oxide semiconductor (xe2x80x9cMOSxe2x80x9d) capacitor coupled by a dummy word line.
All three of the aforementioned designs exhibit similar problems in that the reference generating techniques employed do not track with the actual memory cells. Therefore, because of manufacturing process variations, operating temperature changes and the like, acceptable operating margin will be taken away from both the logic xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d levels.
In accordance with the precharge and reference voltage technique for a DRAM memory array of the present invention, two additional rows of reference cells are added to the array. These identical cells can be used to generate a reference voltage for the reference bit line.
Since the reference cells are identical to the real memory cells, one half VCC needs to be stored (or half way between a logic level xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d) into the reference cell. When the array starts the pre-charge cycle, the regular word line (xe2x80x9cWLxe2x80x9d) and latch P-channel bar (xe2x80x9cLPBxe2x80x9d) signals both turn xe2x80x9coffxe2x80x9d. At this point, the SH1 signal goes xe2x80x9chighxe2x80x9d effectively shorting the complementary bit line pair (xe2x80x9cBLxe2x80x9d and xe2x80x9c/BLxe2x80x9d) together. These two lines will charge share to create a half way level (VCC/2 if xe2x80x9c1xe2x80x9d=VCC and xe2x80x9c0xe2x80x9d=VSS) that will be restored into the reference cell since the reference cell word line (xe2x80x9cXExe2x80x9d (Xeven) or xe2x80x9cXOxe2x80x9d (Xodd)) will still be xe2x80x9chighxe2x80x9d. After this voltage is restored into the reference cell, the SH2 goes xe2x80x9chighxe2x80x9d and the bit lines are fully precharged to ground. During the start of the next active cycle, both the WL and the decoded XE or XO reference cell word lines will go xe2x80x9chighxe2x80x9d to generate the appropriate signal. XE and XO may be decoded with the least significant bit (xe2x80x9cLSBxe2x80x9d) row address.
In an exemplary embodiment disclosed herein, a VSS, or logic level xe2x80x9c0xe2x80x9d bit line precharge sense amplifier is shown in which only the latch P-channel (xe2x80x9cLPxe2x80x9d) and latch P-channel bar (xe2x80x9cLPBxe2x80x9d) nodes are needed. The latch N-channel (xe2x80x9cLNxe2x80x9d) node is shorted to ground. However, the technique of the present invention is likewise applicable to VCC precharged bit lines functioning in a similar fashion with the SH2 signal now operative to instead short the bit lines xe2x80x9chighxe2x80x9d (or to VCC) with the LP node coupled to VCC and latch N-channel bar (xe2x80x9cLNBxe2x80x9d) node now being the active sense clock signal.
It should be noted that, due to the added capacitance of the reference cell being attached to one of the bit lines, the bit lines BL and /BL will not equilibrate to exactly VCC/2. In operation, they will instead equilibrate slightly higher or lower than this value depending on the data that was previously written to the reference cell during the conventional DRAM restore operation. Nevertheless, this effect is small if the bit lines are relatively long as is the case with large DRAM sub-arrays.
Particularly disclosed herein is an integrated circuit device incorporating a dynamic random access memory array. The device comprises at least one sense amplifier; a pair of complementary bit lines coupled to the sense amplifier; a plurality of memory cells coupled to each of the pair of complementary bit lines; at least one reference cell coupled to each of the pair of bit lines, and wherein the reference cell stores a reference voltage level substantially equal to an equilibrated voltage differential between each of the pair of bit lines. A word line is respectively coupled to each of the memory cells for selectively causing a read out of the contents of a corresponding one of the memory cells onto one of the pair of complementary bit lines and a reference cell word line is coupled to each of the reference cells, with the reference cell word line selectively causing the equilibrated voltage level to be stored in an associated one of the reference cells.
Also disclosed herein is a sense amplifier for a dynamic random access memory array including a plurality of memory cells associated with each of a pair of complementary bit lines. The sense amplifier comprises: a latch coupling the pair of complementary bit lines for latching a respective voltage level on each of the bit lines; a first switching device for selectively coupling the complementary bit lines together to establish an equilibrated voltage level; at least one reference cell coupled to each of the pair of complementary bit lines for storing the equilibrated voltage level; and second and third switching devices respectively coupled to one of the pair of said complementary bit lines for coupling the pair of bit lines to a common voltage source.
Still further disclosed herein is a bit line precharge technique for a dynamic random access memory array incorporating at least one sense amplifier coupled to a pair of complementary bit lines, with each of the complementary bit lines being coupled to a plurality of memory cells and at least one reference cell. The technique comprises the steps of: de-asserting a word line signal coupled to at least one of the memory cells; coupling the complementary bit lines together to provide an equilibrated voltage level; storing the equilibrated voltage level in the reference cell and coupling the complementary bit lines to a common voltage level.